AMD EPYC / Instinct MI300A: improper LFENCE serialization allows speculation-barrier bypass

CVSS 5.7CVE-2024-36315Firmware, BMC & network fabriccurated

Impact

LFENCE is not enforced as a full serializing instruction on the affected parts, so software speculation barriers - the mitigation that OS and hypervisor code relies on for Spectre-class defenses - can be stepped past, leaking data across a speculation boundary. This matters on EPYC 9004/8004/4004 hosts and MI300A APU nodes that run untrusted guests or untrusted tenant code on the same socket, because the barriers used to separate those contexts are weaker than assumed. It is a confidentiality-only side channel, local, with high attack complexity - not a direct read primitive. AMD tracks it in bulletins SB-3030 and SB-4017.

Who can reach it

A local authenticated user or guest able to run code on the affected processor and win a side-channel race. No remote path.

What to do

Follow AMD bulletins AMD-SB-3030 and AMD-SB-4017 for the mitigation applicable to your part; where AMD ships updated microcode or AGESA, it reaches the fleet as a BIOS/firmware update, which means scheduling each node out of service for a flash and reboot. The NVD record does not name fixed versions - read the bulletins for your exact SKU before planning the window.

References

https://nvd.nist.gov/vuln/detail/CVE-2024-36315 https://www.amd.com/en/resources/product-security/bulletin/AMD-SB-3030.html https://www.amd.com/en/resources/product-security/bulletin/AMD-SB-4017.html

This entry is curated: imported from vendor advisories with machine assistance, not yet individually verified. Confirm against your vendor's advisory before acting, and report anything wrong.