Intel processors (indirect branch prediction): MULTI-TENANT ISOLATION: Spectre v2: an attacker trains the indirect

Impact

MULTI-TENANT ISOLATION: Spectre v2: an attacker trains the indirect branch predictor so that a victim context - another process, another VM, or the kernel - speculatively executes an attacker-chosen gadget and leaks its memory through a cache side channel. On a shared GPU host this is the canonical cross-VM and container-to-host read primitive, and it is still the reason retpoline, IBPB and eIBRS exist in every kernel you run.

Who can reach it

Local code execution anywhere on the host - any container, any VM. No privilege needed.

What to do

Mitigated by an Intel microcode update plus OS/hypervisor changes. Microcode for this class is normally shipped by your distribution as an early-loadable image, so you can deploy it with a package update and a reboot without waiting for an OEM BIOS release - that distinction is the difference between a week and a quarter. Verify after reboot by reading /sys/devices/system/cpu/vulnerabilities/ rather than assuming the package took effect. On nodes that host untrusted co-tenants, also disable SMT or enforce core scheduling; that costs real throughput and is a capacity-planning decision, not a free toggle.

References