AMD processors - speculative inference of TSC_AUX when reads are disabled: Sibling of the other Transient Scheduler

CVSS 3.8CVE-2024-36349Firmware, BMC & network fabricTSATransient Scheduler Attackcurated

Impact

Sibling of the other Transient Scheduler Attack disclosures. A user process can speculatively infer TSC_AUX even when the platform has disabled that read. TSC_AUX carries the CPU and NUMA node identity, so leaking it tells an attacker exactly where they are running - which is the prerequisite for arranging co-residency with a target tenant and then mounting a cross-core or cross-thread channel against them.

Who can reach it

Local, unprivileged user process on affected AMD parts.

What to do

Mitigated by AMD microcode plus, on most of these, a kernel-side change - and the durable delivery vehicle is the OEM SBIOS/AGESA package, which carries **one to six months of OEM lag** and needs a drained node and a full power cycle. The linux-firmware amd-ucode blobs get you the microcode sooner via initramfs early-load and a reboot, but AMD does not support late-loading microcode on a running EPYC host, so either way this is reboot-required, not a live patch. Ships with the rest of the July 2025 TSA batch; do not cherry-pick individual CVEs out of it. Benchmark after applying - the TSA mitigations add work on privilege transitions.

References

https://nvd.nist.gov/vuln/detail/CVE-2024-36349 https://www.amd.com/en/resources/product-security.html

This entry is curated: imported from vendor advisories with machine assistance, not yet individually verified. Confirm against your vendor's advisory before acting, and report anything wrong.