AMD SEV guest VMs - TLB flush after VMCB creation sequence: The CPU may fail to flush the TLB after a particular

Impact

The CPU may fail to flush the TLB after a particular sequence involving creation of a new VMCB in SEV guest VMs. Stale translations across a VM boundary mean one guest's memory can be reached through another's cached mapping - the low CVSS reflects the difficulty of arranging the sequence, not the severity of what happens if you do.

Who can reach it

Requires a host able to arrange a specific VMCB creation sequence - hypervisor-privileged.

What to do

Fixed in AMD reference firmware (AGESA / PSP / SEV firmware) and delivered only as an OEM SBIOS/BIOS package - Dell, HPE, Supermicro, Lenovo and the ODMs each rebuild and requalify AMD's AGESA drop before shipping. **Expect one to six months of OEM lag**, and on end-of-support platforms expect nothing. Applying it is a drain plus full power cycle, not a driver reload. Verify by reading back the PSP/SMU firmware version afterwards rather than trusting the BIOS version string. This sits inside the SEV-SNP trust boundary, so the update moves the platform's reported TCB version: refresh VCEK certificates from AMD's KDS and update any attestation policy your tenants pin, or confidential guest launches will start failing right after the BIOS lands.

References

Related entries

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