Database/Control plane, storage & DevOps
AMD - Global History Register side channel: A side channel through the branch predictor's Global History Register
Impact
A side channel through the branch predictor's Global History Register, disclosed by Harbin Institute of Technology. Branch history is shared microarchitectural state, so an attacker observes the shape of a co-resident victim's control flow - which for an inference workload can reveal what model is running and what path a request took through it.
Who can reach it
Local, co-resident with the victim.
What to do
**No CVE and no fix** - AMD's response is software best practices. As with the other predictor-state channels, the enforceable control is not co-scheduling mutually untrusted tenants on the same physical core. No patch, no reboot; this is a scheduling and fleet-composition decision.
References
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This entry is curated: imported from vendor advisories with machine assistance, not yet individually verified. Confirm against your vendor's advisory before acting, and report anything wrong.