Linux kernel amdgpu: unvalidated GEM_CREATE domain combinations hit a BUG_ON and panic the node

Impact

AMDGPU_GEM_CREATE checked domain bits against AMDGPU_GEM_DOMAIN_MASK but never validated which combinations make sense. Userspace could combine CPU, GTT or VRAM with DOORBELL, GDS, GWS or OA, so amdgpu_bo_placement_from_domain() builds more placements than AMDGPU_BO_MAX_PLACEMENTS and trips a BUG_ON. A BUG_ON in an ioctl path is an immediate kernel panic, reachable with a single crafted allocation request. On a multi-tenant GPU node this is a one-call denial of service against every job on the box: one tenant's pod takes down the host and everything sharing it, and recovery is a reboot rather than a container restart.

Who can reach it

Local user with access to an amdgpu render node (/dev/dri/renderD*) - i.e. any tenant with a GPU pod. A single ioctl with an invalid domain combination is enough; no authentication or elevated capability required.

What to do

Apply the stable fix, which adds amdgpu_gem_are_domains_valid() and returns -EINVAL for invalid combinations in amdgpu_gem_create_ioctl(). Five stable commits are listed; the record names no fixed release version. Rollout is a patched kernel and a per-node reboot, so drain GPU workloads first. There is no configuration mitigation short of denying tenants direct render-node access.

References

Related entries

• Linux kernel amdgpu display: NULL dereference when vblank is requested on a CRTC with no streamCVE-2026-80542 · Linux kernel amdgpu display core (amdgpu_dm_crtc_set_vblank, CRTC with no stream attached)Unscored
• Linux kernel amdgpu: user-supplied indirect buffer size is unbounded, corrupting ring packet fieldsCVE-2026-80576 · Linux kernel drm/amdgpu (command submission, amdgpu_cs_p2_ib IB size)Unscored
• GPU / accelerator firmware (VBIOS, GSP, NVSwitch): GPU-resident firmware sits below the host OS and is not coveredNCVD-0000-012-gpu-accelerator-firmware-vbios-g · GPU / accelerator firmware (VBIOS, GSP, NVSwitch)Unscored
• NVIDIA Multi-Instance GPU (MIG) partitioning: MIG gives each instance its own SM slice, L2 slice, memory slice andNCVD-2020-001-nvidia-multi-instance-gpu-mig-pa · NVIDIA Multi-Instance GPU (MIG) partitioningUnscored
• NVIDIA Multi-Instance GPU (MIG) partitioning: MIG gives each instance its own SM slice, L2 slice, memory slice andNCVD-2020-003-nvidia-multi-instance-gpu-mig-pa · NVIDIA Multi-Instance GPU (MIG) partitioningUnscored
• Integrated GPU graphics data compression (Intel, AMD, Apple, Arm, Qualcomm, NVIDIA): GPUs apply data-dependent losslessNCVD-2023-003-integrated-gpu-graphics-data-com · Integrated GPU graphics data compression (Intel, AMD, Apple, Arm, Qualcomm, NVIDIA)Unscored