Intel SGX (L1 terminal fault on enclave pages): Speculative execution lets code outside an enclave read the enclave's

CVSS 7.3CVE-2018-3615Firmware, BMC & network fabricForeshadowL1TF-SGXcurated

Impact

Speculative execution lets code outside an enclave read the enclave's data out of the L1 data cache, breaking the confidentiality guarantee SGX exists to provide. On a confidential-compute offering this is the whole product failing: the host, or a co-resident tenant with the right sibling-thread placement, reads enclave secrets including sealing and attestation material.

Who can reach it

Local code execution on the same physical core as the enclave. In a cloud that includes a co-tenant on a sibling hyperthread, which is why the mitigation story involves disabling SMT.

What to do

Microcode update plus OS/hypervisor mitigations. Intel microcode for this can be late-loaded at boot by the OS without waiting for an OEM BIOS release, so the practical path is: update the microcode package, reboot, and disable SMT (or enforce core scheduling) on nodes that run untrusted co-tenants. Also re-attest and re-provision any enclave secrets that existed on unpatched hardware - the microcode fix does not un-leak them.

References

https://nvd.nist.gov/vuln/detail/CVE-2018-3615 https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00161.html

This entry is curated: imported from vendor advisories with machine assistance, not yet individually verified. Confirm against your vendor's advisory before acting, and report anything wrong.